- Digital isolator application notes pdf#
- Digital isolator application notes plus#
- Digital isolator application notes series#
The emergence of capacitive-coupled digital isolators presents a new solid-state solution to driving synchronous rectifiers.įigure 1 shows a functional drawing of a digital isolator, the ISO721M. Some topologies lend themselves to implementing self-driven synchronous rectifiers, where the gate drive signals are derived directly from the power transformer. While less common, optocouplers are sometimes used. Gate drive transformers are the most popular method of accomplishing this.
The control signals must bridge the isolation boundary with minimal delay.
In isolated topologies, the power-supply controller typically is located on the primary side of the isolation barrier, while the synchronous rectifiers are located on the secondary side.
Digital isolator application notes pdf#
To download the PDF version of this article, click here.Many of today’s switching power supplies implement synchronous rectifiers to improve efficiency. Bikiran received his MS in Electrical Engineering from Stanford University. His area of expertise is in designing iCoupler digital isolation products aimed at the standard data isolation devices and communication buses. Mark received his MS in physics from Indiana University.īikiran Goswami is a mixed-signal integrated circuit design engineer for the iCoupler Digital Isolator Group at Analog Devices Inc. He is also responsible for agency safety certifications for all iCoupler digital isolator products. His area of expertise is iCoupler digital isolation products, including isoPower isolated power supply devices and communications bus devices such as I2C and USB isolators. The digital isolation technology provides significant advantages over the older optocoupler because of the tight control of skew between channels and other distortions in the signal chain.Ībout the author Mark Cantrell is a staff applications engineer for the iCoupler Digital Isolator Group at Analog Devices Inc. This method will provide a boost to the max SPI clock rate across the available isolation technologies. The delayed clock scheme presented here provides a path to improving the throughput of an isolated SPI interface and increase sample rates. The delay mismatch is not only considerably minimised but also well defined across wide operating conditions and is guaranteed in the datasheet by the DCLK ERR parameter.Ĭonclusion In order for oversampling to be a useful tool in increasing dynamic range in sensor applications, there must be a high enough multiplier of the sampling frequency compared to the frequency of interest to provide significant noise reduction. The delay cell is carefully trimmed at production to match the round-trip prop delay through the part, thereby minimising the timing mismatch between delayed-clock and returning slave data. Figure 6 shows the internal block diagram of the ADuM3150. The DCLK is generated by delaying the standard SPI clock by an amount equal to the round trip propagation delay through the isolator. The ADuM3150 generates a delayed clock, DCLK, without the use of an extra isolator channel.
Digital isolator application notes series#
The ADuM3150 ( figure 6) is part of the SPIsolator series of high-speed digital isolators designed to optimise the isolation of SPI buses. Optimising the digital isolator delayed clock implementation Analogue Devices has developed a digital isolator optimised to deliver the highest possible performance in the delayed clock scheme. Thus, using existing isolators will cost more power and board space while still falling short of the maximum possible benefit of the scheme. The extra isolator to delay the clock still consumes around 20-25% more power. The half SPI clock period will be 鈮? ns or 20 ns, resulting in an even faster maximum clock rate of 25MHz.Īlthough the speed and skews of the digital isolators are significantly better than that of optocouplers, timing skews and distortions between channels still limit the maximum possible SPI clock rate. In these cases there is an added benefit. In such three-wire SPI buses, a single quad digital isolator with two reverse channels can be used to implement the SPI bus and the delayed clock. In many applications, the MCU only shifts out data from an ADC and doesn't shift in anything.
Given similar timing through all isolator channels, the new SPI half clock period should be 鈮? ns or 25 ns, for a maximum clock rate of 20MHz.
Digital isolator application notes plus#
This prevents isolator prop delay from limiting overall SPI throughput, and now a faster SPI clock is possible that's limited only by mismatches and distortion between the clock and data channels, plus trace, master, and slave delays. Consider implementing a delayed clock with an extra isolator channel as per figure 4-at a minimum an additional high speed channel needs to be used.
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